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The Distributed Array Processor (DAP) produced by International Computers Limited (ICL) was the world's first commercial massively parallel computer. The original paper study was complete in 1972 and building of the prototype began in 1974. The first machine was delivered to Queen Mary College in 1979. ==Development== The initial 'Pilot DAP' was designed and implemented by Dr Stewart F Reddaway with the aid of David J Hunt and Peter M Flanders at the ICL Stevenage Labs. Their manager and a major contributor was John K Iliffe who had designed the Basic Language Machine - he is better known nowadays for Iliffe vectors. The ICL DAP had 64x64 single bit processing elements (PEs) with 4096 bits of storage per PE. It was attached to an ICL mainframe and could be used as normal memory. Programs for the DAP were written in DAP FORTRAN which was FORTRAN extended with 64x64 matrix and 64 element vector primitives. It had a Single Instruction Multiple Data (SIMD) architecture. Each operation could be performed under the control of a mask which controlled which elements were affected. Array programs were executed as subroutines of normal mainframe FORTRAN programs and IO was handled by the mainframe. Operationally, there was an overhead to transfer computational data into and out of the array, and problems which did not fit the 64x64 matrix imposed additional complexity to handle the boundaries (65x65 was perhaps the worst case!) – but for problems which suited the architecture, it could outperform the current Cray pipeline architectures by two orders of magnitude. The ICL 2980 was not a popular machine and this held back the use of the DAP as an attached processor was restricted initially to this one range. The design as described in Stewart's 1973 paper is pretty much that which was implemented in the first commercial version except the facility to supply address bits from the processing elements was removed. This change greatly simplified hardware error detection. A notable extra facility was carry propagation to simplify vector mode addition. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「ICL Distributed Array Processor」の詳細全文を読む スポンサード リンク
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